(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to methods used to form lightly doped source/drain (LDD) regions for metal oxide semiconductor field effect transistor (MOSFET) devices.
(2) Description of Prior Art
Lightly doped source/drain (LDD) regions have been used to improve MOSFET device reliability via a reduction of a hot electron injection phenomena. However as MOSFET or complimentary metal oxide semiconductor (CMOS) technology advances into 0.10 μm generation and beyond there is a need to reduce the possibility of compensation of the already narrow channel region that can occur via lateral diffusion of the adjacent LDD implanted dopants. Offset insulator spacers formed on the sides of a conductive gate structure prior to formation of the LDD region do offer the desired additional spacing between the channel and LDD implanted regions. The use of offset spacers however increase device fabrication costs via the use of additional process steps such as deposition of the offset spacer insulator layer as well as the dry etch procedure needed to define the offset spacers.
The present invention will describe methods of offsetting the LDD implanted regions from the MOSFET channel region without formation of offset insulator spacers thus avoiding the additional process costs inherent in the definition of the insulator offset spacers. This invention will describe the formation of conductive gate structures featuring specific edge profiles which will allow the LDD implanted regions to be offset from the channel region, accomplished without additional process steps. Prior art such as Fang et al, in U.S. Pat. No. 6,514,830 B1, Yu et al, in U.S. Pat. No. 6,350,639, B1, Chan et al, in U.S. Pat. No. 6,025,240, Lin et al, in U.S. Pat. No. 6,187,644 B1, and Lin et al, in U.S. Pat. No. 6,294,432 B1, describe methods of forming offset insulator spacers as well as methods of forming ion implanted LDD regions. None of the above prior art however describe the novel procedures featured in the present invention in which the edge profile of a conductive gate structure is specifically engineered and then used to offset an LDD region subsequently formed via ion implantation procedures.